Exploration of Ambient Energy Harvesting Nonvolatile Processor: From Circuit to    System

主讲人：     刘勇攀博士

清华大学电子工程系副教授

清华大学电路与系统研究所所长

时  间：2016年5月10日（星期二）上午9:30-11:00

地  点：北二区教学楼二层大会议室

主 办 单 位： 信息工程学院

主讲人介绍：:

Dr. Yongpan Liu is an associate professor in Tsinghua University. He has been a visiting scholar at Penn State University during summer 2014. He is a key member of Tsinghua-Rohm Research Center and Research Center of Future ICs. His research interests include low power design, emerging circuits and systems and design automation. He published over 60 papers and designed several sensor chips, including the first nonvolatile processor (THU1010N). He is an IEEE senior member and served on TPC of (DAC, ASP-DAC, ISLPED, A-SSCC, ICCD, VLSI-D, VLSI-DAT, etc) and has received Design Contest Awards from (ISLPED2012, ISLPED2013) and best paper award of HPCA2015. He served as the publicity co-chair of ICCD15, IoTSym of ESWEEK15 and the exhibition chair of A-SSCC15 and one of the founders of Asia Workshop on Smart Sensor System.

内容介绍: 

Energy harvesting has been widely investigated as a promising method of providing power for ultra-low-power applications. Such energy sources include solar energy, radio- frequency (RF) radiation, piezoelectricity, thermal gradients, etc. However, the power supplied by these sources is highly unreliable and dependent upon ambient environment factors. Hence, it is necessary to develop specialized systems that are tolerant to this power variation, and also capable of making forward progress on the computation tasks. With the emerging memory technologies, nonvolatile processors are manufactured with nonvolatile registers and can work reliably under the environments with frequency power interrupts, such as energy harvesting and wireless powered applications. This talk first presents the motivation of nonvolatile processor design and defines the metrics for such transient computing systems. Furthermore, we will illustration the nonvolatile processor from circuit, architecture and system levels. Finally, the latest chip design efforts are reported and future research opportunities and challenges will be given out for collaborations.